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| hc05bd7grs/h rev 2.0 68HC05BD7 68hc705bd7 68hc05bd2 specification rev 2.0 (general release) january 20, 1998 technical operation taiwan taipei, taiwan f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page i mc68HC05BD7 r ev. 2 . 0 general release specification table of contents section 1 general description .............................................. 1 1.1 features......................................................................................1 1.1.1 hardware features................................................................1 1.1.2 software features .................................................................3 1.2 signal description.......................................................................7 1.2.1 vdd and vss........................................................................7 1.2.2 irq/vpp................................................................................7 1.2.3 extal, xtal ........................................................................7 1.2.3.1 crystal oscillator..............................................................7 1.2.4 reset ..................................................................................8 1.2.5 pa0-pa7................................................................................8 1.2.6 pb0-pb5................................................................................8 1.2.7 pc0*/pwm8*-pc1*/pwm9* ..................................................8 1.2.8 pc2/pwm10/adc0- pc5/pwm13/adc3 .............................8 1.2.9 pc6/pwm14/vsyno, pc7/pwm15/hsyno .......................8 1.2.10 pd0*/sda*, pd1*/scl* ........................................................8 1.2.11 pd2***/clamp, pd3*/sog ..................................................8 1.2.12 pwm0**-pwm7** ..................................................................9 1.2.13 hsync, vsync ...................................................................9 1.3 options .......................................................................................9 section 2 memory ....................................................................... 11 2.1 cop ..........................................................................................15 2.2 rom .........................................................................................15 2.3 eprom.....................................................................................15 2.4 ram..........................................................................................15 section 3 cpu core..................................................................... 17 3.1 registers...................................................................................17 3.1.1 accumulator (a)...................................................................17 3.1.2 index register (x) ...............................................................18 3.1.3 stack pointer (sp)...............................................................18 3.1.4 program counter (pc) ........................................................18 3.1.5 condition code register (ccr) ..........................................18 3.1.5.1 half carry bit (h-bit) ......................................................19 3.1.5.2 interrupt mask (i-bit) ......................................................19 3.1.5.3 negative bit (n-bit) ........................................................19 3.1.5.4 zero bit (z-bit) ...............................................................19 3.1.5.5 carry/borrow bit (c-bit) .................................................19 section 4 interrupts................................................................. 21 4.1 cpu interrupt processing .........................................................21 4.2 reset interrupt sequence.........................................................23 4.3 software interrupt (swi) ...........................................................23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page ii general release specification mc68HC05BD7 r ev. 2 . 0 4.4 hardware interrupts.................................................................. 23 4.4.1 external interrupt (irq)....................................................... 23 4.4.2 vsync interrupt ................................................................. 24 4.4.3 ddc12ab interrupt ............................................................. 24 4.4.4 multi-function timer interrupt (mft) .................................. 25 section 5 resets..........................................................................27 5.1 external reset (reset) .......................................................... 27 5.2 internal resets ......................................................................... 27 5.2.1 power-on reset (por) ...................................................... 27 5.2.2 computer operating properly reset (copr)..................... 27 5.2.3 illegal address (iladr) reset ............................................ 28 section 6 operating modes ....................................................29 6.1 user mode................................................................................ 29 6.2 self-check mode............................................................... 29 6.3 bootstrap mode ........................................................................ 29 6.4 mode entry ............................................................................... 29 6.5 eprom programming.............................................................. 30 6.5.1 programming sequence ..................................................... 30 6.5.2 programming control register (pcr) ................................ 31 6.6 low power modes.................................................................... 31 6.6.1 stop instruction................................................................. 31 6.6.2 wait instruction ................................................................. 31 6.7 cop watchdog timer considerations ..................................... 32 section 7 input/output ports ................................................33 7.1 port a ....................................................................................... 33 7.2 port b ....................................................................................... 33 7.3 port c ....................................................................................... 33 7.4 port d ....................................................................................... 33 7.5 input/output programming ....................................................... 34 7.6 port c and d configuration register........................................ 35 section 8 pulse width modulation......................................37 8.1 operation of 8-bit pwm ........................................................... 37 8.2 open-drain option register..................................................... 38 section 9 ddc12ab interface .................................................39 9.1 introduction............................................................................... 39 9.2 ddc12ab features.................................................................. 39 9.3 registers .................................................................................. 40 9.3.1 ddc address register (dadr) .......................................... 40 9.3.2 ddc control register (dcr) .............................................. 40 9.3.3 ddc master control register (dmcr) ............................... 41 9.3.4 ddc status register (dsr)................................................ 43 9.3.5 ddc data transmit register (ddtr)................................. 44 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page iii mc68HC05BD7 r ev. 2 . 0 general release specification 9.3.6 ddc data receive register (ddrr)..................................44 9.4 data sequence .........................................................................45 9.5 program algorithm....................................................................45 section 10 sync processor...................................................... 49 10.1 introduction ...............................................................................49 10.2 functional blocks......................................................................49 10.2.1 polarity detection ................................................................49 10.2.2 sync signal counters..........................................................49 10.2.3 polarity controlled hsyno/vsyno outputs ......................49 10.2.4 clamp pulse output ..........................................................50 10.3 registers...................................................................................51 10.3.1 sync processor control and status register (spcsr) ......51 10.3.2 sync processor input/output control register (spiocr) ..52 10.3.3 vertical frequency registers (vfrs)..................................53 10.3.4 hsync frequency registers (hfrs)....................................54 10.4 system operation .....................................................................54 section 11 multi-function timer............................................. 57 11.1 introduction ...............................................................................57 11.2 register ....................................................................................57 11.2.1 multi-function timer control/status register .......................57 11.2.2 mft timer counter register...............................................59 section 12 a/d converter.......................................................... 61 12.1 introduction ...............................................................................61 12.2 input..........................................................................................61 12.2.1 adc0-adc3 ........................................................................61 12.3 registers...................................................................................62 12.3.1 adc control/status register ...............................................62 12.3.2 adc channel register ........................................................62 12.4 program example .....................................................................63 section 13 electrical specifications.................................. 65 13.1 maximum ratings .....................................................................65 13.2 thermal characteristics............................................................65 13.3 dc electrical characteristics ....................................................66 13.4 control timing ..........................................................................67 13.5 ddc12ab timing....................................................................68 13.5.1 ddc12ab interface input signal timing .............................68 13.5.2 ddc12ab interface output signal timing ..........................68 13.6 hsync/vsync input timing ...................................................69 section 14 mechanical specifications ................................ 71 14.1 introduction ...............................................................................71 14.2 40-pin dip package (case 711-03) .........................................71 14.3 42-pin sdip package (case 858-01) .......................................71 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page iv general release specification mc68HC05BD7 r ev. 2 . 0 section 15 application diagram .............................................73 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page v mc68HC05BD7 r ev. 2 . 0 general release specification list of figures figure 1-1: mc68HC05BD7 block diagram .....................................................................4 figure 1-2: mc68HC05BD7/bd2 40-pin dip pin assignment .........................................5 figure 1-3: mc68HC05BD7/bd2 42-pin sdip pin assignment.......................................6 figure 1-4: oscillator connections ...................................................................................7 figure 2-1: the 16k memory map of the mc68HC05BD7.............................................11 figure 2-2: mc68HC05BD7 i/o register $00-$0f.........................................................12 figure 2-3: mc68HC05BD7 i/o register $10-$1f.........................................................13 figure 2-4: mc68HC05BD7 i/o register $20-$2f.........................................................14 figure 3-1: mc68hc05 programming model .................................................................17 figure 4-1: interrupt processing flowchart ....................................................................22 figure 4-2: external interrupt..........................................................................................24 figure 6-1: mode entry diagram ....................................................................................30 figure 6-2: wait flowcharts..........................................................................................32 figure 7-1: port i/o circuitry...........................................................................................34 figure 8-1: pwm data register .....................................................................................37 figure 8-2: relationship between 5-bit pwm and 3-bit brm........................................38 figure 8-3: pwm open-drain option register...............................................................38 figure 9-1: software flowchart of slave mode interrupt routine...................................47 figure 9-2: software flowchart in master mode: (a) mode setup. (b) interrupt routine..48 figure 10-1: clamp output waveform ...........................................................................50 figure 12-1: structure of a/d converter.........................................................................61 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page vi general release specification mc68HC05BD7 r ev. 2 . 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page vii mc68HC05BD7 r ev. 2 . 0 general release specification list of tables table 4-1: vector address for interrupts and reset .......................................................21 table 6-1: mode select summary ..................................................................................30 table 7-1: i/o pin functions...........................................................................................35 table 9-1: pre-scaler of master clock baudrate ............................................................42 table 11-1: cop reset rates and rti rates................................................................59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page viii general release specification mc68HC05BD7 r ev. 2 . 0 this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 1 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 1 general description the mc68HC05BD7 hcmos microcontroller is a member of the m68hc05 family of low- cost single-chip microcontrollers. it is particularly suitable as multi-sync computer monitor controller. this 8-bit microcontroller unit (mcu) contains an on-chip oscillator, cpu, ram, rom, ddc12ab module, parallel i/o, pulse width modulator, multi-function timer, 6-bit adc, and sync processor. 1.1 features 1.1.1 hardware features hc05 core low cost, hcmos technology 40-pin dip and 42-pin sdip packages 256 bytes of ram for hc05bd2 384 bytes of ram for hc05bd7hc705bd7 5.75k-bytes of user rom for hc05bd2 11.75k-bytes of user rom for hc05bd7 11.5k-bytes of user eprom for hc705bd7 26 bidirectional i/o lines: 14 dedicated and 12 multiplexed i/o lines. 4 of the 14 dedicated i/o lines and 6 of the 12 multiplexed i/o lines have max. +12v or +5v open-drain output buffers 16 x 8-bit pwm channels: two 8-bit pwm channels have +12v open- drain outputs: 8 dedicated 8-bit pwm channels have +5v open-drain output options 6-bit adc with 4 selectable input channels multi-function timer (mft) with periodic interrupt sync signal processor module for processing horizontal, vertical, composite, and sog sync signals; frequency counting; polarity detection; polarity controlled hsyno and vsyno or extracted vsync outputs, and clamp pulse output ddc12ab ? module contains ddc1 hardware and multi-master i 2 c ?? hardware for ddc2ab protocol software maskable edge-sensitive or edge and level-sensitive external interrupt ? ddc is a standard defined by vesa. ?? i 2 c-bus is a proprietary philips interface bus. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 2 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary cop watchdog reset power-on reset power saving wait mode; stop mode not implemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 3 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 1.1.2 software features similar to mc6800 8 x 8 unsigned multiply instruction efficient use of program space versatile interrupt handling software programmable external interrupt options true bit manipulation addressing modes with indexed addressing for tables efficient instruction set memory mapped i/o upward software compatible with the mc146805 cmos family f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 4 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary figure 1-1: mc68HC05BD7 block diagram pb0 pb1 pb2* pb3* pb4* pb5* oscillator and divide by 2 data dir reg port b reg extal xtal core timer (cop) ram 256 bytes for hc05bd2 384 bytes for hc05bd7 384 bytes for hc705bd7 5.75k-bytes rom for hc05bd2 11.75k-bytes rom for hc05bd7 11.5k-bytes eprom for hc705bd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 data dir reg port a reg pc0*/pwm8* pc1*/pwm9* pc2/pwm10/adc0 pc3/pwm11/adc1 pc4/pwm12/adc2 pc5/pwm13/adc3 pc6/pwm14/vsyno pc7/pwm15/hsyno data dir reg port c reg reset irq /vpp pulse width modulation (pwm) sync processor hsync vsync vdd vss stk ptr cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 1 1 0 0 0 0 0 alu 68hc05 cpu accum program counter cpu registers ddc12ab pwm0** pwm1** pwm2** pwm3** pwm4** pwm5** pwm6** pwm7** port d reg data dir reg pd1*/scl* pd0*/sda* ddc12ab pwm/adc/hvprocessor *: +12v open-drain pd3*/sog pd2***/clamp 6-bit adc **: +5v open-drain option sp ***: +5v open-drain irq /vpp: vpp valid for hc705 version only, not used for hc05 version f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 5 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary figure 1-2: mc68HC05BD7/bd2 40-pin dip pin assignment pa1 pa0 pa2 pd0*/sda* pd1*/scl* pwm7** pc4/pwm12/adc2 pc3/pwm11/adc1 pc2/pwm10/adc0 pc1*/pwm9* pc0*/pwm8* pwm5** pc7/pwm15/hsyno pc6/pwm14/vsyno pc5/pwm13/adc3 pwm6** vsync hsync pwm3** pwm4** 40-pin dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 xtal pa5 pa6 pa3 pa4 pb4* pb3* pb2* pb1 pa7 extal pb5* irq /vpp pb0 vdd vss reset pwm0** pwm1** pwm2** *: +12v open-drain **: +5v open-drain option mc68HC05BD7 irq /vpp: vpp valid for hc705 version only, not used for hc05 version f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 6 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary figure 1-3: mc68HC05BD7/bd2 42-pin sdip pin assignment pa1 pa0 pa2 pd0*/sda* pd1*/scl* pwm7** pc4/pwm12/adc2 pc3/pwm11/adc1 pc2/pwm10/adc0 pc1*/pwm9* pc0*/pwm8* pwm5** pc7/pwm15/hsyno pc6/pwm14/vsyno pc5/pwm13/adc3 pwm6** vsync hsync pwm3** pwm4** 42-pin sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 41 xtal pa5 pa6 pa3 pa4 pb4* pb3* pb2* pb1 pa7 extal pb5* irq /vpp pb0 vdd vss reset pwm0** pwm1** pwm2** 21 42 *: +12v open-drain pd2***/clamp pd3*/sog **: +5v open-drain option ***: +5v open-drain option mc68HC05BD7 irq /vpp: vpp valid for hc705 version only, not used for hc05 version f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 7 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 1.2 signal description 1.2.1 vdd and vss vdd is the positive supply pin and vss is the ground pin. 1.2.2 irq/ vpp this pin has two functions. while in user mode, this pin serves as irq , a general purpose interrupt input which is software programmable for two choices of interrupt triggering sensitivity. these options are: 1) negative edge-sensitive triggering only, or 2) both negative edge-sensitive and level-sensitive triggering. in the latter case, either type of input to the irq pin will produce the interrupt. this interrupt can be inhibited by setting the inhirq bit in the mft register. while in bootstrap mode, this pin is used as vpp pin for hc705 version. it is used to supply high voltage needed for programming the user eprom. 1.2.3 extal, xtal the extal and xtal pins are the connections for the on-chip oscillator. the extal, and xtal pins can accept the following sets of components: 1. a crystal as shown in figure 1-4(a) 2. an external clock signal as shown in figure 1-4(b) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . 1.2.3.1 crystal oscillator the circuit in shows figure 1-4(a) a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturer? recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an internal start-up resistor of approximately 2 m w is provided between extal and xtal for the crystal type oscillator. figure 1-4: oscillator connections mcu 36 pf (a) crystal or ceramic resonator connections extal xtal 36 pf unconnected external clock (b) external clock source connection extal xtal mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 8 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 1.2.4 reset this active low input-only pin is used to reset the mcu to a known start-up state. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 5 for more details. 1.2.5 pa0-pa7 these eight i/o lines comprise port a. the state of any pin is software programmable and all port a lines are configured as inputs during reset. see section 7 for a detailed description of i/o programming. 1.2.6 pb0-pb5 these six i/o lines comprise port b. the state of any pin is software programmable and all port b lines are configured as inputs during reset. pb2 to pb5 are +12v open-drain pins. see section 7 for a detailed description of i/o programming. 1.2.7 pc0*/pwm8*-pc1*/pwm9* these two +12v open-drain pins are either 8-bit pwm channels 8 to 9 outputs or general purpose i/o port c. the state of any pin is software programmable and all port c lines are configured as inputs during reset. see section 7 for a detailed description of i/o programming. 1.2.8 pc2/pwm10/adc0- pc5/pwm13/adc3 these four pins can be selected as general purpose i/o of port c, pwm or adc input channel 0-2. see section 7 for how to configure the pins. also see section 8 and section 12 for a detailed description of these modules. 1.2.9 pc6/pwm14/vsyno, pc7/pwm15/hsyno these two pins can be selected as general purpose i/o of port c, pwm or sync signal outputs. see section 7 for how to configure the pins. also see section 8 and section 10 for a detailed description of these modules. 1.2.10 pd0*/sda*, pd1*/scl* these pins are either general purpose i/o pins of port d or the data line (sda) and clock line (scl) of ddc12ab. these two pins are open-drain pins. see section 7 for how to configure the pins. see section 9 for a detailed description. 1.2.11 pd2***/clamp, pd3*/sog the pd2*** is +5v open-drain general purpose i/o pin and the pd3* is +12v open-drain general purpose i/o pin. the pd2 pin could become the clamp pulse push-pull output to pre-amp ic and the pd3 pin could become the sog digital input of the sync processor when the corresponding enable bit in spiocr register is set. these two pins will not be bonded out in 40-pin dip package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 9 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 1.2.12 pwm0**-pwm7** these pins are dedicated for 8-bit pwm channels 0 to 7, which have +5v open-drain software options. see section 8 for a detailed description. 1.2.13 hsync, vsync these two input pins are for video sync signals input from the host computer. the signals will be used for video mode detection and output to hsyno and vsyno . the host computer can also send a composite sync signal to the hsync input. this composite signal will be separated internally. the polarity of the input signals can be either positive or negative. these two pins contain internal schmitt triggers as part of their inputs to improve noise immunity. see section 10 for a detail description. 1.3 options mc68HC05BD7 provides an option for irq interrupt edge only sensitivity or edge and level sensitivity and one option register for individual pwm channels 0 to 7 to be programmed as open-drain type output. the irq option is selected by setting the appropriate bit in the mftcsr register at address $0008 and the pwm open-drain option register is located at address $0012. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 1: general description page 10 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 2: memory page 11 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 2 memory the mc68HC05BD7 has a 16k byte memory map, consisting of user rom/eprom, ram, self-check/bootstrap rom, and i/o as shown in figure 2-1 . figure 2-1: the 16k memory map of the mc68HC05BD7 stack 64 bytes self-check/bootstrap vectors 16 bytes ram 256 bytes for hc05bd2 384 bytes for hc05bd7/hc705bd7 $0000 i/o 48 bytes $00c0 $0100 $01b0 unused 480 bytes bootstrap rom for hc705bd7 unused in hc05bd2/hc05bd7 user vectors 16 bytes $3ff0 $3fff $3fe0 $0030 $2800 $3f00 $0e00 $1000 224 bytes self-check rom for hc05bd2/hc05bd7 unused in hc705bd7 $0fe0 user rom 5.57k-bytes for hc05bd2 11.75k-bytes for hc05bd7 user eprom 11.5k-bytes for hc705bd7 $3e00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 2: memory page 12 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary figure 2-2: mc68HC05BD7 i/o register $00-$0f configuration reg 2 cr2 port d data portd w r pc6 hfh2 hfh3 hfh0 hfh1 $0003 $0002 port c data portc w r vf0 read write $0000 port a data porta w r pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 $0001 port b data portb w r $0004 port a data direction ddra w r ddra0 ddra1 ddra2 ddra3 ddra4 ddra5 ddra6 ddra7 $0009 addr 1 0 2 3 4 5 6 7 register $000c w r unimplemented $0005 port b data direction ddrb w r $0006 port c data direction ddrc w r $0007 $000a vert frequency low reg vflr $000b hor frequency high reg hfhr $000d w r $000e $000f pb0 pb1 vf3 vf5 vf2 vf6 pb2 pb3 pb4 pb5 pc0 pc1 pc2 pc3 pc4 pc5 pc7 ddrb0 ddrb1 ddrb2 ddrb3 ddrb4 ddrb5 ddrc0 ddrc1 ddrc2 ddrc3 ddrc4 ddrc5 ddrc6 ddrc7 vf7 vf4 vf1 hfh6 hover hfh4 hfh5 sp control & status spcsr port d data direction ddrd w r ddrd0 ddrd1 pd0 pd1 configuration reg 1 cr1 r pwm8 pwm9 pwm10 pwm11 pwm12 pwm13 pwm14 w r adc2 w r hinvo vsie vedge vpol hpol w r vf8 vf9 vert frequency high reg vfhr $0008 mft ctrl/status reg mftcsr w r tof rtif tofie rtie irqn rt0 rt1 mftcr2 mftcr3 mftcr0 mftcr1 mft timer counter reg mftcr w r mftcr6 mftcr7 mftcr4 mftcr5 reserved vf10 vf11 w 0 vof 0 vf12 pd3 pd2 ddrd2 ddrd3 hsyno vsyno adc1 adc0 vsif comp vinvo scl sda pwm15 inhirq adc3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 2: memory page 13 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary figure 2-3: mc68HC05BD7 i/o register $10-$1f tc8 reserved unimplemented ddc master control reg dmcr read write $0010 $0011 $0014 $0019 w r addr 1 0 2 3 4 5 6 7 register $001c unimplemented $0012 $0013 $0015 unimplemented $0016 adc control/status reg w r $0017 adc channel register w r $0018 w r $001a $001b $001d $001e w r $001f tc10 tc9 tc11 tc12 tc13 tc15 tc14 reserved for eprom control pcr w r unimplemented w r w r hfl2 hfl3 hfl0 hfl1 w r w r hor frequency low reg hflr sp io control reg spiocr 0 0 hfl4 0 pwm open-drain option register w r reserved drd7 drd0 ddc data receive reg ddrr ddc data transmit reg ddtr w r w r drd1 drd5 drd4 drd3 drd2 drd6 den ddc status register dsr w r txak dien ddc control register dcr w r dad7 ddc address register dadr w r dad1 dad5 dad4 dad3 dad2 dad6 sclien ddc1en dtd7 dtd0 dtd1 dtd5 dtd4 dtd3 dtd2 dtd6 sclif rxak match txbe rxbf ad0 ad1 ad5 ad4 ad3 ad2 result chsl0 chsl1 clamp sout rw txif rxif 7pwmo 6pwmo 5pwmo 4pwmo 3pwmo 2pwmo 1pwmo 0pwmo extad alif nakif bb mast mrw br2 br1 br0 sogin bpor coinv hsyncs vsyncs pgm elat f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 2: memory page 14 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary figure 2-4: mc68HC05BD7 i/o register $20-$2f read write addr 1 0 2 3 4 5 6 7 register unimplemented $002f pulse width modulator 15pwm w r $002e pulse width modulator 14pwm w r $002d pulse width modulator 13pwm w r 13brm0 13brm1 13brm2 13pwm0 13pwm1 13pwm2 13pwm3 13pwm4 $002c pulse width modulator 12pwm w r 12brm0 12brm1 12brm2 12pwm0 12pwm1 12pwm2 12pwm3 12pwm4 $002a pulse width modulator 10pwm w r 10brm0 10brm1 10brm2 10pwm0 10pwm1 10pwm2 10pwm3 10pwm4 $0029 pulse width modulator 9pwm w r 9brm0 9brm1 9brm2 9pwm0 9pwm1 9pwm2 9pwm3 9pwm4 $002b pulse width modulator 11pwm w r 11brm0 11brm1 11brm2 11pwm0 11pwm1 11pwm2 11pwm3 11pwm4 $0028 pulse width modulator 8pwm w r 8brm0 8brm1 8brm2 8pwm0 8pwm1 8pwm2 8pwm3 8pwm4 $0027 pulse width modulator 7pwm w r 7brm0 7brm1 7brm2 7pwm0 7pwm1 7pwm2 7pwm3 7pwm4 $0026 pulse width modulator 6pwm w r 6brm0 6brm1 6brm2 6pwm0 6pwm1 6pwm2 6pwm3 6pwm4 $0025 pulse width modulator 5pwm w r 5brm0 5brm1 5brm2 5pwm0 5pwm1 5pwm2 5pwm3 5pwm4 $0023 pulse width modulator 3pwm w r 3brm0 3brm1 3brm2 3pwm0 3pwm1 3pwm2 3pwm3 3pwm4 $0022 pulse width modulator 2pwm w r 2brm0 2brm1 2brm2 2pwm0 2pwm1 2pwm2 2pwm3 2pwm4 $0024 pulse width modulator 4pwm w r 4brm0 4brm1 4brm2 4pwm0 4pwm1 4pwm2 4pwm3 4pwm4 $0021 pulse width modulator 1pwm w r 1brm0 1brm1 1brm2 1pwm0 1pwm1 1pwm2 1pwm3 1pwm4 $0020 pulse width modulator 0pwm w r 0brm0 0brm1 0brm2 0pwm0 0pwm1 0pwm2 0pwm3 0pwm4 reserved 14brm0 14brm1 14brm2 14pwm0 14pwm1 14pwm2 14pwm3 14pwm4 15brm0 15brm1 15brm2 15pwm0 15pwm1 15pwm2 15pwm3 15pwm4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 2: memory page 15 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 2.1 cop the cop time-out is prevented by writing a ??to bit 0 of address $3ff0. see section 11 for detail. 2.2 rom for mc68HC05BD7, the user rom consists of 11.75k bytes of rom from $1000 through $3eff and 16 bytes of user vectors from $3ff0 through $3fff. for mc68hc05bd2, the user rom consists of 5.75k bytes of rom from $2800 through $3eff and 16 bytes of user vectors from $3ff0 through $3fff. the self-check rom is located from $3f00 through $3fe0 and self-check vectors are located from $3fe0 through $3fef. 2.3 eprom for mc68hc705bd7, the user eprom consists of 11.5k bytes of eprom from $1000 through $3dff and 16 bytes of user vectors from $3ff0 through $3fff. the bootstrap rom is located from $0e00 through $0fdf and bootstrap vectors are located from $3fe0 through $3fef, at the same location as self-check vectors. 2.4 ram the user ram consists of 384 bytes from $0030 to $01af for hc05bd7/hc705bd7. user ram consists of 256 bytes from $30 to $12f for hc05bd2. the stack pointer can access 64 bytes of ram from $00ff to $00c0. see section 3.1.3, stack pointer (sp) . note: using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 2: memory page 16 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 3: cpu core page 17 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 3 cpu core the mc68HC05BD7 has a 16k memory map. therefore it uses only the lower 14 bits of the address bus. in the following discussion the upper 2 bits of the address bus can be ignored. the stack has only 64 bytes. therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00c0 and then wrap-around to $00ff. all other instructions and registers behave as described in this chapter. 3.1 registers the mcu contains five registers which are hard-wired within the cpu and are not part of the memory map. these five registers are shown in figure 3-1 and are described in the following paragraphs. figure 3-1: mc68hc05 programming model 3.1.1 accumulator (a) the accumulator is a general purpose 8-bit register as shown in figure 3-1 . the cpu uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. the accumulator is not affected by a reset of the device. condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter h nzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 3: cpu core page 18 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 3.1.2 index register (x) the index register shown in figure 3-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu finds the operand address by adding the index register content to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu finds the operand address by adding the index register content to a 16-bit immediate value. the index register can also serve as an auxiliary accumulator for temporary storage. the index register is not affected by a reset of the device. 3.1.3 stack pointer (sp) the stack pointer shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k bytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. when accessing memory, the ten most significant bits are permanently set to 0000000011. the six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 ($40) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack and an interrupt uses five locations. 3.1.4 program counter (pc) the program counter shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k bytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched. normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.1.5 condition code register (ccr) the ccr shown in figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. the fifth bit is the interrupt mask. these bits can be individually tested by a program, and specific actions can be taken as a result of their states. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower five bits of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 3: cpu core page 19 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 3.1.5.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. 3.1.5.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), or wait instructions. 3.1.5.3 negative bit (n-bit) the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often tested flag by assigning the flag to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag. 3.1.5.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. 3.1.5.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is neither set by an inc nor by a dec instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 3: cpu core page 20 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 4: interrupts page 21 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 4 interrupts 4.1 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is cleared) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. otherwise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appropriate interrupt software service routine from the vector table at locations $3ff0 thru $3fff as defined in table 4-1 . table 4-1: vector address for interrupts and reset an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. register n/a n/a n/a spcsr dmcr dsr mftcsr n/a n/a flag n/a n/a n/a vsif txif rxif alif nakif sclif tof rtif n/a n/a interrupts reset software external interrupt vsint ddc12ab interrupt timer overflow real time interrupt n/a n/a cpu int reset swi irq sp ddc12ab mft n/a n/a vector adds. $3ffe-$3fff $3ffc-$3ffd $3ffa-$3ffb $3ff8-$3ff9 $3ff6-$3ff7 $3ff4-$3ff5 $3ff2-$3ff3 $3ff0-$3ff1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 4: interrupts page 22 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary figure 4-1: interrupt processing flowchart n n n y y y y y from reset is i-bit set? load interrupt vectors to pc set i-bit in ccr pc -> (sp,sp-1) x -> (sp-2) a -> (sp-3) cc -> (sp-4) clear irq latch restore registers from stack cc, a, x, pc irq external interrupt? ddc12ab interrupt? execute instruction fetch next instruction rti instruction? swi instruction? n n y v sync interrupt? n y mft interrupt? n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 4: interrupts page 23 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 4.2 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner. a low level input on the reset pin or an internally generated reset signal causes the program to vector to its starting address which is specified by the contents of $3ffe and $3fff. the i-bit in the condition code register is also set. the mcu is configured to a known state during this type of reset as described in section 5 . 4.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), the swi instruction executes after interrupts which were pending before the swi was fetched, or before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of $3ffc and $3ffd. 4.4 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are four types of hardware interrupts which are explained in the following sections. 4.4.1 external interrupt (irq ) if the irq option is edge and level sensitive triggering (irqn=0), a low level at the irq pin and a cleared interrupt mask bit of the condition code register will cause an external interrupt to occur. if the mcu has finished with the interrupt service routine, but the irq pin is still low, the external interrupt will start again. in fact, the mcu will keep on servicing the external interrupt as long as the irq pin is low. if the irq pin goes low for a while and resumes to high (a negative pulse) before the interrupt mask bit is cleared, the mcu will not recognize there was an interrupt request, and no interrupt will occur after the interrupt mask bit is cleared. if the irq option is negative edge sensitive triggering (irqn=1), a negative edge occurs at the irq pin and a cleared interrupt mask bit of the condition code register will cause an external interrupt to occur. if the mcu has finished with the interrupt service routine, but the irq pin has not returned back to high, no further interrupt will be generated. the interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) only. if the negative edge occurs while the interrupt mask bit is set, the interrupt signal will be latched, and interrupt will occur as soon as the interrupt mask bit is cleared. the latch will be cleared by reset or cleared automatically during fetch of the external interrupt vectors. therefore, one (and only one) external interrupt edge could be latched while the interrupt mask bit is set. if the inhirq bit in the mft register is set, no irq interrupt can be generated. the service routine address is specified by the contents of $3ffa and $3ffb. figure 4-2 shows the two methods for the interrupt line (irq ) to be recognized by the processor. the first method is single pulses on the interrupt line spaced far apart enough to be serviced. the minimum time between pulses is a function of the number of cycles required to execute f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 4: interrupts page 24 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary the interrupt service routine plus 21 cycles. once a pulse occurs, the next pulse should not occur until the mcu software has exited the routine (an rti occurs). the second configuration shows several interrupt line ?ire-anded?to perform the interrupts at the processor. thus, if after servicing one interrupt and the interrupt line remains low, then the next interrupt is recognized. note: irqn is located at bit 3 of the multi-function timer register at $0008, and is cleared by reset. figure 4-2: external interrupt 4.4.2 vsync interrupt the vsync interrupt is generated when a specific edge of vsync input is detected as described in section 10 . the interrupt enable bit, vsie, for the vsync interrupt is located at bit 7 of sync processor control and status register (spcsr) at $000c. the i- bit in the ccr must be cleared in order for the vsync interrupt to be enabled. this interrupt will vector to the interrupt service routine located at the address specified by the contents of $3ff8 and $3ff9. the vsync interrupt flag (vsif) must be cleared by writing ??to it in the interrupt routine. 4.4.3 ddc12ab interrupt the ddc12ab interrupt is generated by the ddc12ab circuit as described in section 9 . the interrupt enable bit for the ddc12ab interrupt is located at bit 6 of ddc12ab control register (dcr) at $0018. the i-bit in the ccr must be cleared in order for the ddc12ab interrupt to be enabled. this interrupt will vector to the interrupt service routine located at the address specified by the contents of $3ff6 and $3ff7. irq irq1 irqn irq (mcu) t ilih t ilil t ilih edge-sensitive trigger condition the minimum pulse width tilih is one the period tilil should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 cycles level-sensitive trigger condition if after servicing an interrupt, the irq normally used with pull-up resistor for remains low, then the next interrupt is recognized. wire-ored connection internal bus period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 4: interrupts page 25 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 4.4.4 multi-function timer interrupt (mft) there are two different multi-function timer (mft) interrupt flags that will cause an interrupt whenever they are set and enabled. the interrupt flags and enable bits are located in the mft control and status register. either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of $3ff4 and $3ff5. see section section 11, multi-function timer for more informations on mft interrupts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 4: interrupts page 26 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 5: resets page 27 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 5 resets the mcu can be reset from four sources? external and 3 internal: external reset pin power-on-reset (por) computer operating properly watchdog reset (copr) illegal address reset (iladr) 5.1 external reset (reset ) the reset pin is the only external reset source. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. termination of the external reset input can alter the operating mode of the mcu. note: activation of the rst signal is generally referred to as reset of the device, unless otherwise specified. 5.2 internal resets the three internally generated resets are the initial power-on reset, the cop watchdog timer reset, and the illegal address reset 5.2.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power-on condition and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4065 internal processor bus clock cycles (ph2) after the oscillator becomes active. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this 4065 cycles delay, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.2 computer operating properly reset (copr) the internal copr reset is generated automatically (if enabled) by a time-out of the cop watchdog timer. this time-out occurs if the counter in the cop watchdog timer is not reset (cleared) within a specific time by a program reset sequence. refer to section 11 for more information on this time-out feature. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 5: resets page 28 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 5.2.3 illegal address (iladr) reset the mcu monitors all opcode fetches. if an illegal address is accessed during an opcode fetch, an internal reset is generated. illegal address space consists of all unused locations within the memory space and the i/o registers. (see figure 2-1 : the 16k memory map of the mc68HC05BD7 .) because the internal reset signal is used, the mcu comes out of an iladr reset in the same operating mode it was in when the opcode was fetched. the iladr reset is disabled in test (non user) mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 6: operating modes page 29 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 6 operating modes the hc05bd7/hc05bd2 has the following operating modes: single-chip mode (scm) and self-check mode. the hc705bd7 has the following operating modes: user mode and bootstrap mode. 6.1 user mode in this mode, all address and data bus activity occurs within the mcu so no external pins are required for these functions. 6.2 self-check mode in this mode, the reset vector is fetched from the 240-byte internal self-check rom at $3f00:$3fef. the self-check rom contains a self-check program to test the functions of internal modules. 6.3 bootstrap mode in this mode, the reset vector is fetched from the 480-byte internal bootstrap rom at $0e00:$0fdf. the bootstrap rom contains a small program which reads a program into internal ram and then passes control to execute eprom programming. 6.4 mode entry the mode entry is done at the rising edge of the reset pin. once the device enters one of the operating modes, the mode can only be changed by an external reset. at the rising edge of the reset pin, the device latches the states of irq and pb5 pins and places itself in the specified mode. while the reset pin is low, all pins are configured as single chip mode. the following table shows the states of irq and pb5 pins for each mode entry. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 6: operating modes page 30 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary table 6-1: mode select summary figure 6-1: mode entry diagram 6.5 eprom programming the 11.5k bytes of user eprom is positioned at $1000 through $3dff with the vector space from $3ff0 to $3fff. the erased state of eprom is read as $ff and eprom power is supplied from vpp and vdd pins. the programming control register (pcr) is provided for the eprom programming. the function of eprom depends on the device operating mode. in the user mode, elat and pgm bits in the pcr are available for the user read/write and the remaining test bits become read only bits. please contact motorola for programming boards availability. 6.5.1 programming sequence the eprom programming is as follows: - set the elat bit - write the data to the address to be programmed - set the pgm bit - delay for the appropriate amount of time - clear the pgm and the elat bit the last item may be done on a single cpu write. it is important to remember that an external programming voltage must be applied to the vpp pin while programming, but it should remain between vdd and vss during normal operation. mode reset irq pb5 user mode self check/bootstrap l or h v tst x h v tst = 1.8 x vdd v tst = 1.8 x v dd h = v dd l = v ss h l v tst h l h l reset irq pb5 single chip mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 6: operating modes page 31 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 6.5.2 programming control register (pcr) program control register is provided for eprom programming the device. elat?prom latch control 0 - eprom address and data bus configured for normal read. 1 - eprom address and data bus configured for programming (writes to eprom cause address and data to be latched). eprom is in programming mode and can not be read. this bit is not writable to 1 when no vpp voltage is applied to the vpp pin. pgm?prom program command 0 - programming power to eprom array is switched off. 1 - programming power to eprom array is switched on. 6.6 low power modes the mc68HC05BD7 has only one low-power operational mode. the wait instruction provides the only mode that reduces the power required for the mcu by stopping cpu internal clock. the wait instruction is not normally used if the cop watchdog timer is enabled. the stop instruction is not implemented in its normal sense . the stop instruction will be interpreted as the nop instruction by the cpu if it is ever encountered. the flow of the wait mode is shown in figure 6-2 . 6.6.1 stop instruction since the execution of a normal stop instruction results in the stoppage of clocks to all modules, including the cop watchdog timer, this instruction is hence not implemented in its usual way to make cop watchdog timer meaningful in monitor applications. execution of the stop instruction will be the same as that of the nop instruction. hence, i bit in the condition code register will not be cleared. 6.6.2 wait instruction in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. other internal clocks remain active, permitting interrupts to be generated from the multi-function timer, or a reset to be generated from the cop watchdog timer. the timer may be used to generate a periodic exit from the wait mode. execution of the wait instruction automatically clears the i-bit in the condition code register, so that any hardware interrupt can wake up the mcu. all other registers, memory, and input/output lines remain in their previous states. 0 7 elat 0000000 6543210 pgm w r pcr $001d reset t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 6: operating modes page 32 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 6.7 cop watchdog timer considerations the cop watchdog timer is always enable in mc68HC05BD7. it will reset the mcu when it times out. for a system that must have intentional uses of the wait mode, care must be taken to prevent such situations from happening during normal operations by arranging timely interrupts to reset the cop watchdog timer. figure 6-2: wait flowcharts y y n n n y y 1.fetch reset vector or 2.service interrupt a.stack b.set i-bit c.vector to interrupt routine internal cop reset? external oscillator active, and internal timer clock active restart internal processor clock stop internal processor clock, clear i-bit in ccr external h/w interrupt? external reset? wait n internal interrupt? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 7: input/output ports page 33 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 7 input/output ports in the user mode there are 26 bidirectional i/o lines arranged as 4 i/o ports (port a, b, c, and d). the individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (ddrs). also, if enabled by software, port c and d will have additional functions as pwm outputs, ddc i/o and sync signal processor outputs. 7.1 port a port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $00 and the data direction register (ddr) is at $04. reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 7.2 port b port b is a 6-bit bidirectional port which does not share any of its pins with other subsystems. pb2 to pb5 are +12v open-drain port pins. the port b data register is at $01 and the data direction register (ddr) is at $05. reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 7.3 port c port c is an 8-bit bidirectional port which shares pins with pwm, sync processor, and adc subsystem. see section 8 for a detailed description of pwm, section 10 for a detailed description of sync processor, and section 12 for a detailed description of adc. these pins are configured as pwm outputs when the corresponding bits in the configuration register 1 are set. pc6 and pc7 are configured to vsyno and hsyno outputs when the corresponding bits in the configuration register 2 are set. and pc2 to pc5 are configured as adc input channels as the corresponding bit in the configuration register 2 are set. if there is any confliction between the two configuration registers, the configuration register 2 has higher priority. the port c data register is at $02 and the data direction register (ddr) is at $06. reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port to output mode. 7.4 port d port d is a 4-bit bidirectional port. pd0 and pd1 shares their pins with ddc12ab subsystem. see section 9 for a detailed description of ddc12ab. these two pins are configured to the corresponding functions when the corresponding bits in the configuration register 2 are set. they have open-drain output and hysteresis input level to improve noise immunity. pd2 is a +5v open-drain general i/o pin which f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 7: input/output ports page 34 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary shares its pin with the clamp output. see section 10 for the description of clamp signal. it becomes the clamp output when the clamp bit in spiocr register is set. pd3 is a +12v open-drain i/o pin which shares its pin with the sog input. also see section 10 for the description of sog input. it is configured as sog input when the sog bit in spiocr register is set. the port d data register is at $03 and the data direction register (ddr) is at $07. reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 7.5 input/output programming bidirectional port lines may be programmed as an input or an output under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set. a pin is configured as an input if its corresponding ddr bit is cleared. during reset, all ddrs are cleared, which configure all port pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. see figure 7-1 and . figure 7-1: port i/o circuitry i/o pin read data write data data register bit internal hc05 data bus reset (rst) read/write ddr data direction register bit output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 7: input/output ports page 35 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary table 7-1: i/o pin functions note: a ?litch?can be generated on an i/o pin when changing it from an input to an output unless the data register is first pre-conditioned to the desired state before changing the corresponding ddr bit from a zero to a one. 7.6 port c and d configuration register port c and port d are shared with pwm, adc, ddc12ab, and sync processor. the configuration registers at $0a and $0b are used to configure those i/o pins. they are default to zero after power-on reset. setting these bits will set the corresponding pins to the corresponding functions. for example, setting scl and sda bits of register $0b will configure port d pins 1 and 0 as ddc12ab pins, regardless of ddr1 and ddr0 settings. when any pwm8-pwm15 bits of cr1 register are set, the corresponding pins of port c become the pwm output if the corresponding bits in cr2 register are clear. when the pin is defined as pwm channel, it become an output only pin. when any adc3-adc0 bits of the cr2 register are set, the corresponding pins of port c become the adc input channels. when hsyno or vsyno is set, the pc2 or pc3 becomes the output of hsync or vsync accordingly, see section 10 for the detail description of hsyno and vsyno outputs. when scl and sda bits of the cr2 register are set, the ddc12ab use these two pins as clock and data pins. in summary, the configuration in the cr2 register has higher priority than in the cr1 register. r/w ddr i/o pin functions 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. w r cr1 $000a reset pwm15 0 7 00 54 0 0000 6 3210 pwm14 pwm11 pwm10 pwm9 pwm8 pwm13 pwm12 w r cr2 $000b reset 0 7 00 54 0 0000 6 3210 adc2 scl sda adc1 adc0 hsyno vsyno adc3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 7: input/output ports page 36 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 8: pulse width modulation page 37 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 8 pulse width modulation there are 16 pwm channels. channel 0 to channel 7 are dedicated pwm channels with 5v open-drain option. channel 8 to channel 15 are shared with ports c under the control of the corresponding configuration register. the channel 8 and channel 9 are 12v open- drain outputs. 8.1 operation of 8-bit pwm each 8-bit pwm channel is composed of an 8-bit register which contains a 5-bit pwm in msb portion and a 3-bit binary rate multiplier (brm) in lsb portion. there are 16 data registers as shown in figure 8-1 located from $20 to $2f. the value programmed in the 5- bit pwm portion will determine the pulse length of the output. the clock to the 5-bit pwm portion is the mcu clock and the repetition rate of the output is hence 62.5 khz at 2 mhz mcu clock. the 3-bit brm will generate a number of narrow pulses which are equally distributed among an 8-pwm-cycle frame. the number of pulses generated is equal to the number programmed in the 3-bit brm portion. an example of the waveform is shown in figure 8-2 . combining the 5-bit pwm together with the 3-bit brm, the average duty cycle at the output will be (m+n/8)/32, where m is the content of the 5-bit pwm portion, and n is the content of the 3-bit brm portion. using this mechanism, a true 8-bit resolution pwm type dac with reasonably high repetition rate can be obtained. figure 8-1: pwm data register the value of each pwm data register is continuously compared with the content of an internal counter to determine the state of each pwm channel output pin. double buffering is not used in this pwm design. 0pwm3 0pwm1 0pwm4 0 7 0brm1 0brm2 0pwm0 0000000 6543210 0pwm2 w r pwmr $20-$2f reset t 0brm0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 8: pulse width modulation page 38 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary figure 8-2: relationship between 5-bit pwm and 3-bit brm 8.2 open-drain option register this pwm open-drain option register contains 8 bits which are programmed to change the output drive of individual pwm channel from channel 0 to channel 7 to be open-drain type. this register is located at $0012 figure 8-3: pwm open-drain option register when any bit in this register is one, the corresponding pwm channel output becomes +5v open-drain type. when the bit is zero, the corresponding pwm channel has push-pull output. all eight bits are clear upon reset. 32 t m = $00 m = $01 m = $0f m = $1f narrow pulse possibly inserted by the brm t = 1 mcu clock period (0.5 m s if mcu clock = 2 mhz) pwm cycles in which narrow pulses are inserted in an 8-cycle frame 4 2, 6 1, 3, 5, 7 xx1 x1x 1xx n 6pwmo 4pwmo 7pwmo 0 7 1pwmo 2pwmo 3pwmo 0000000 6543210 5pwmo w r pwmor $12 reset t 0pwmo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 39 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 9 ddc12ab interface 9.1 introduction this ddc12ab interface module is mainly used for monitor to show its identification information to video controller. it contains ddc1 hardware and a two-wire, bidirectional serial bus which is fully compatible with multi-master iic bus protocol to support ddc2ab interface. in ddc1 type of communication, the module is in transmit mode. for ddc2ab protocol, the module can be either in transmit mode or in receive mode upon host? commands. when ddc1 hardware is enabled, the loaded data is serially clocked out to sda line by the rising edge of vsync input signal continuously. if ddc2 protocol is selected, the module will act as a standard iic module, and will response only when it is addressed or in master mode. during ddc1 communication, the falling transition in the scl line can be detected to interrupt cpu for mode switching. this module not only can be applied in ddc12ab communication, but also can be used as one typical command reception serial bus for factory setup and alignment purpose. it also provides the flexibility of hooking additional devices to an existing system in future expansion without adding extra hardware. this ddc12ab module uses the scl clock line and the sda data line to communicate with external ddc host or iic interface. these two pins are shared with pd0 and pd1 port pins. the outputs of sda and scl pins are all open-drain type. it means no clamping diode connected between the pin and internal vdd. the maximum data rate typically is 100k bps. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. 9.2 ddc12ab features ddc1 hardware fully compatible with multi-master iic bus standard software controllable acknowledge bit generation interrupt driven byte by byte data transfer calling address identification interrupt auto detection of rw bit and switching of transmit or receive mode accordingly detection of start, repeated start, and stop signals auto generation of start and stop condition in master mode arbitration loss detection and no-ack awareness in master mode master clock generator with 8 selectable baud rates automatic recognition of the received acknowledge bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 40 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 9.3 registers there are six different registers used in the ddc12ab module and the internal configuration of these registers is discussed in the following paragraphs. 9.3.1 ddc address register (dadr) dad7-dad1 bit 7-bit 1 these 7 bits can be the ddc2 interface? own specific slave address in slave mode or the calling address when in master mode. so the program must update it as the calling address while entering the master mode and restore its own slave address after the master mode is quitted. this register is cleared as $a0 upon reset. extad bit 0 the extad bit is set to expand the calling address of this module. when it is one, the module will acknowledge the general call address $00 and the address comparison circuit will only compare the 4 msb bits in the dadr register. for example, the dadr contains $a1, that means extad is enabled and the calling address is $a0, therefore, the module can acknowledge the calling address of $00 and $a0 to $af. when it is clear, the module will only acknowledge to the specific address which is stored in the dadr register. it is clear upon reset. 9.3.2 ddc control register (dcr) the dcr provides five control bits. dcr is cleared upon reset. den bit 7 if the ddc module enable bit (den) is set, the ddc module is enabled. if the den is clear, the interface is disabled and all flags will restore its power-on default states. reset clears this bit. dien bit 6 if the ddc interrupt enable bit (dien) is set, the interrupt occurs provided the txif or rxif in the status register is set or the alif or nakif in the dmcr register is set and the i-bit in the condition code register is cleared. if dien is cleared, the interrupt of txif, rxif, alif, and nakif are all disabled. reset clears this bit. dad7 1 7 dad1 0100000 6543210 dad4 w r dadr $0017 reset dad5 dad6 dad2 dad3 extad 0 7 0xx000x 6543210 w r dcr $0018 reset t txak den dien sclien ddc1en f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 41 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary txak bit 3 if the transmit acknowledge enable bit (txak) is cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving 8 data bits. when txak is set, no acknowledge signal will be generated at the 9th clock (i.e., acknowledge bit = 1). reset clears this bit. sclien bit 2 if the scl interrupt enable bit (sclien) is set, the interrupt occurs provided the sclif in the status register is set and the i-bit in the condition code register is cleared. if sclien is cleared, the interrupt of sclif is disabled. reset clears this bit. ddc1en bit 1 when ddc1 protocol enable (ddc1en) is set, the vsync input will be selected as clock input of ddc module. its rising edge will continuously clock out the data in the shift register. no calling address comparison is performed. the rw bit in the status register will be fixed to be one. if this bit is clear, the sclif bit in the status register is also cleared. reset clears this bit. 9.3.3 ddc master control register (dmcr) the dmcr contains two interrupt flags, one bus status flag, two master mode control bits, and three baudrate select bits. alif bit 7 the arbitration loss interrupt flag is set when software attempt to set mast but the bb has been set by detecting the start condition on the lines or when the ddc12ab module is transmitting a ?ne?to sda line but detected a ?ero?from sda line in master mode, which is so called arbitration loss. this bit can generate an interrupt request to cpu when the dien bit in dcr register is set and i-bit in the condition code register is clear. this bit is cleared by writing ??to it or by reset. nakif bit 6 the no acknowledge interrupt flag is only set in master mode when there is no acknowledge bit detected after one data byte or calling address is transferred. this bit can generate an interrupt request to cpu when the dien bit in dcr register is set and i-bit in the condition code register is clear. this bit is cleared by writing ??to it or by reset. bb bit 5 the bus busy flag is set after a start condition is detected, and is reset when a stop condition is detected. this bit can supplement the software in initiating the master mode protocol. reset clears this bit. 0 7 0000000 6543210 w r dmcr $0016 reset t mrw alif nakif br2 br1 bb mast br0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 42 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary mast bit 4 if the software set the master control bit, the module will generate a start condition to the sda and scl lines and send out the calling address which is stored in the dadr register. but if the alif flag is set when arbitration loss occurs on the lines, the module will discard the master mode by clearing the mast bit and release both sda and scl lines immediately. this bit can also be cleared by writing zero to it or when the nakif is set. when the mast bit is cleared either by nakif set or by software, not by alif set, the module will generate the stop condition to the lines after the current byte transmission is done. reset clears this bit. mrw bit 3 this mrw bit will be transmitted out as the bit 0 of the calling address when the module sets the mast bit to enter the master mode. it will also determine the transfer direction of the following data bytes. when it is one, the module is in master receive mode. when it is zero, the module is in master transmit mode. reset clears this bit. br2-br0 bit 2-bit 0 the three baud rate select bits will select one of eight clock rates as the master clock when the module is in master mode. the serial clock frequency is equal to the cpu clock divided by the divider shown in following table. for the cpu clock will be halted while program executes the wait instruction, program must not enter wait mode when the ddc12ab module is in master mode in order not to hang up the communication on the lines. these bits are cleared upon reset. table 9-1: pre-scaler of master clock baudrate br2:br1:br0 divider 0 : 0 : 0 0 : 0 : 1 0 : 1 : 0 0 : 1 : 1 1 : 0 : 0 1 : 0 : 1 1 : 1 : 0 1 : 1 : 1 20 40 80 160 320 640 1280 2560 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 43 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 9.3.4 ddc status register (dsr) this status register is readable only. all bits are cleared upon reset except bit 3 (rxak) and bit 1 (txbe). rxif bit 7 the data receive interrupt flag (rxif) is set after the ddrr is loaded with a newly received data. once the ddrr is loaded with received data, no more received data can be loaded to the ddrr register. the only way to release the ddrr register for loading next received data is that software reads the data from the ddrr register to clear rxbf flag. this bit is cleared by writing ??to it or when the den is disabled. txif bit 6 the data transmit interrupt flag is set before the data of the ddtr register is downloaded to the shift register. it is software? responsibility to fill the ddtr register with new data when this bit is set. this bit is cleared by writing ??to it or when the den is disabled. match bit 5 the match flag is set when the received data in the ddrr register is an calling address which matches with the address or its extended addresses (extad=1) specified in the dadr register. srw bit 4 the slave rw bit will indicate the data direction of ddc protocol. it is updated after the calling address is received in the ddc2 protocol. when it is one, the master will read the data from ddc module, so the module is in transmit mode. when it is zero, the master will send data to the ddc module, the module is in receive mode. when ddc1en is set, the srw bit will be one. the reset state of it is zero. rxak bit 3 if the received acknowledge bit (rxak) is low, it indicates an acknowledge signal has been received after the completion of 8 data bits transmission on the bus. if rxak is high, it indicates no acknowledge signal has been detected at the 9th clock. then the module will release the sda line for the master to generate ?top?or ?epeated start?condition. it is set upon reset. sclif bit 2 this sclif flag is set by the falling edge of scl line only when ddc1en is enabled. this bit is cleared by writing zero to it, clearing ddc1en bit or when the den is disable. 0 7 txbe 0001010 6543210 rxbf w r dsr $0019 reset t sclif match rxak srw txif rxif f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 44 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary txbe bit 1 the transmit buffer empty (txbe) flag indicates the status of the ddtr register. when the cpu writes the data into the ddtr register, the txbe flag will be cleared. and it will be set again after the data of the ddtr register has been loaded to the shift register. it is default to be set when the den is disable and will be cleared by writing data to the ddtr register when the den is enabled. rxbf bit 0 the receive buffer full (rxbf) flag indicates the status of the ddrr register. when the cpu reads the data from the ddrr register, the rxbf flag will be cleared. and it will be set after the data or matched address is transferred from the shift register to the ddrr register. it is cleared when den is disabled or ddrr register is read when den is enabled. 9.3.5 ddc data transmit register (ddtr) the data written into this register after den is enabled will be automatically downloaded to the shift register when the module detects the calling address is matched and the bit 0 of the received data is one or when the data in the shift register has been transmitted with received acknowledge bit, rxak =0. so if the program doesn? write the data into the ddtr register ( txbe is cleared) before the matched calling address is detected, the module will pull down the scl line. if the cpu write a data to the ddtr register, then the written data will be downloaded to the shift register immediately and the module will release the scl line, then the txbe is set again and the txif flag is set to generate another interrupt request for data. so the cpu may need to write the next data to the ddtr register to clear txbe flag and for the auto downloading of data to the shift register after the data in the shift register is transmitted over again with rxak =0. if the master receiver doesn? acknowledge the transmitted data, rxak =1, the module will release the sda line for master to generate ?top?or ?epeated start?conditions. the data stored in the ddtr register will not be downloaded to the shift register until next calling from master ( txbe remains unchanged). 9.3.6 ddc data receive register (ddrr) the ddc data receive register ( ddrr ) contains the last received data when the match flag is zero or the calling address from master when the match flag is one. the ddrr register will be updated after a data byte is received and the rxbf is zero. it is a read-only register. the read operation of this register will clear the rxbf flag. after the rxbf flag is dtd7 1 7 dtd0 1111111 6543210 dtd4 w r ddtr $001a reset t dtd5 dtd6 dtd2 dtd3 dtd1 drd7 0 7 drd0 0000000 6543210 drd4 w r ddrr $001b reset t drd5 drd6 drd2 drd3 drd1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 45 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary cleared, the register can load the received data again and set the rxif flag to generate interrupt request for reading the newly received data. 9.4 data sequence 9.5 program algorithm the figure 9-1 shows the algorithm of slave mode interrupt routine of ddc12b protocol. the figure 9-2 shows the algorithm of master mode setup and interrupt service routine. when the ddc module detects an arbitration loss in master mode, it will release both sda and scl lines immediately. but if there is no further "stop condition" detected, the module will be hanged up. so it is recommended to have time-out software to recover from such ill condition. the software can start the time-out counter by looking at the bb (bus busy) in the bit 5 of dmcr and reset the counter when the completion of one byte transmission. if the time-out occurred, program can clear den bit to release the bus, and then set den bit start address 0 ack tx data1 ack tx datan nak stop txbe=0 mast=1 txif=1 txbe=1 mrw=0 txif=1 txbe=1 nakif=1 mast=0 txbe=0 start address 1 ack rx data1 ack rx datan nak stop rxbf=0 mast=1 rxif=1 rxbf=1 rxif=1 rxbf=1 nakif=1 start address 1 ack tx data1 ack tx datan nak stop txbe=0 rxbf=0 rxif=1 rxbf=1 txif=1 txbe=1 start address 0 ack rx data1 ack rx datan nak stop txbe=0 rxbf=0 rxif=1 rxbf=1 rxif=1 rxbf=1 rxif=1 rxbf=1 mast=0 a) master transmit mode b) master receive mode c) slave transmit mode txif=1 txbe=1 match=1 d) slave receive mode match=1 srw=0 srw=1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 46 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary and ddc1en bit to clear bb flag (this is the only way to clear bb flag by software while the module is hanged up due to no "stop condition" received). the program can resume iic master mode after clearing the bb flag and ddc1en bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 47 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary figure 9-1: software flowchart of slave mode interrupt routine sclif =1? clr ddc1en clr sclien clr sclif write data to ddtr txif =1? clear txif write data to ddtr txbe =1? match =1? address received srw =1? rxif =1? clear rxif read data from ddrr write txak for next byte receive y n y n y n y n n y n y rti interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 9: ddc12ab interface page 48 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary figure 9-2: software flowchart in master mode: (a) mode setup. (b) interrupt routine ddtr <= $ff mast <= 0 *restore dadr *restore dadr reset bb =1? read or write ? mrw<=0 ddtr <= 1st data y n read write (a) master mode setup interrupt alif =1? y n nakif =1? y n txif =1? y n mrw =1? y n end of data? y n clr txif end of data? y n clear alif set "failure" flag for retry *restore dadr clr nakif set "incomplete" flag for retry ddtr <= next data clear rxif read ddrr next data is the last? n y txak <= 1 *restore dadr rti (b) master mode interrupt routine wait mrw<=1 *** txak is 1 when master want receive only one byte sei cli den <= 1 dien <= 1 dadr <= txad** txak <= 0 or 1*** ** txad means transmit address * restore its own specific slave address rxif =1? n y mast<=1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 49 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 10 sync processor 10.1 introduction the functions of the module include polarity detection, horizontal frequency counter, vertical frequency counter, and polarity controllable hsyno and vsyno outputs of various input sources, such as separate h & v, composite sync from hsync , sync-on-green, or internal free running h & v pulses. besides, it also provides the clamp pulse output to the external pre-amp chip. the sogin bit in spiocr register will determine the composite sync input pin. all hsync , vsync , and sog inputs have internal schmitt trigger to improve noise immunity. 10.2 functional blocks 10.2.1 polarity detection the hsync polarity detection circuit will measure the length of high period of hsync inputs. if the length of high is longer than 7us and the length of low is shorter than 6us, the hpol bit will be zero, indicates negative polarity. if the length of low is longer than 7us and the length of high is shorter than 6us, the hpol bit is one, positive polarity. the vsync polarity detection circuit perform the similar structure with hsync polarity detection circuit. if the length of high is longer than 4ms and the length of low is shorter than 2ms, the vpol bit will be zero, indicates negative polarity. if the length of low is longer than 4ms and the length of high is shorter than 2ms, the vpol bit is one, positive polarity. both hsync and vsync polarity flags are read-only, and will not affect any internal circuitry. when the comp bit in spcsr register is set, the hpol bit will be the same as vpol bit which is detected under the criteria stated in previous statements. 10.2.2 sync signal counters there are two counters (horizontal frequency counter and vertical frequency counter) to count the number of horizontal sync pulses within 32ms period and the number of system clock cycles between two vertical sync pulses. these two data can be read by the cpu to check the signal frequencies and can be used to determine the video mode. the 13-bit vertical frequency register encompasses vertical frequency range from about 15 hz to 127 hz. due to the asynchronous timing between incoming vsync and internal processor clock, there will be 1 count error on the reading from the register for the same vertical frequency. the horizontal counter counts the pulses on hsync pin, and is uploaded to the $0f and $10 registers every 32.768ms. the step unit in the lower 5-bit register is 0.3125khz. and the least 7 bits in the hfhr register shows the number of khz of incoming hsync signal. the msb of the hfhr is the overflow flag of h-counter, which will be cleared when the register is read by cpu. 10.2.3 polarity controlled hsyno/vsyno outputs the input hsync and vsync signal can be output to pc6 and pc7 when the configuration bit of pc6 and pc7 in register $0b are set for sync output. two f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 50 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary corresponding polarity control bits, bit 3 and bit 2 of register $0c, can change the polarity of hsyno / vsyno outputs. the result hsyno and vsyno outputs can vary while the setting in spcsr and spiocr register is different. if the comp bit in spcsr register is set, the incoming composite sync signal will be the hsyno output and the extracted vsync with 6~7us delay will be the vsync output. when the sout bit in spiocr register is set, the internal free-running 55.556khz with 2us pulse will be the hsyno output and the other free-running 72.34hz with 108us pulse will be the vsyno output. 10.2.4 clamp pulse output the logic will generate a 0.5us - 0.75us pulse at either the leading edge or the trailing edge which is specified by the bpor bit in the spiocr register. see figure 10-1 for its detail timing relation. one control bit to invert the output polarity of clamp pulse is located at bit 5 of spiocr . figure 10-1: clamp output waveform hsync (hpol=1) clamp (bpor=0) clamp (bpor=1) hsync (hpol=0) clamp (bpor=0) clamp (bpor=1) 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 51 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 10.3 registers there are five registers associated with the sync processor module as described below. 10.3.1 sync processor control and status register (spcsr) note: please don? use bset or bclr to manipulate this register when vsie is set and i-bit is clear, or it will cuase abnormal reset. vsie bit 7 when vsync interrupt enable (vsie) bit is set, the vsif flag is enabled to generate an interrupt request to the cpu. when vsie is cleared, the vsif flag is prevented from generating an interrupt request. reset clears this bit. vedge bit 6 the vedge bit specifies the triggering edge of vsync interrupt. when it is zero, the rising edge of internal vsync signal which is either from the vsync pin or extracted from the composite input signal will set vsif flag. when it is one, the falling edge of internal vsync signal will set vsif flag. reset clears this bit. vsif bit 5 this flag is a read-only bit and is set by the specified edge of internal vsync signal which is either from the vsync pin or extracted from the composite input signal. the triggering edge is specified by the vedge bit, see the above description of vedge for details. it is cleared by writing a zero to it or reset. comp bit 4 this composite video input enable bit is set to enable the separator circuit which extracts the vsync pulse from composite input in hsync pin. the extracted vsync pulse will be fed into the vertical counter, vertical polarity detection circuit, and vsyno output circuit as well. its measurable timing is the same as the separate vsync pin input. reset clears this bit. vinvo bit 3 this bit controls the output polarity of the vsyno signal. when it is zero, the vsyno output is identical to the vsync input. when it is one, the inverted vsync signal is output to vsyno pin. 0 7 0000000 6543210 w r spcsr $000c reset t vsif comp vedge vsie vpol hpol hinvo vinvo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 52 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary hinvo bit 2 this bit controls the output polarity of the hsyno signal. when it is zero, the hsyno output is identical to the hsync input. when it is one, the inverted hsync signal is output to hsyno pin. vpol bit 1 this bit shows the polarity of vsync input. if it is one, the vsync input has positive polarity. if it is zero, the vsync input has negative polarity. reset clears this bit. hpol bit 0 this bit shows the polarity of hsync input. if it is one, the hsync input has positive polarity. if it is zero, the hsync input has negative polarity. reset clears this bit. 10.3.2 sync processor input/output control register (spiocr) vsyncs bit 7 the vsyncs bit reflects the logical state of vsync input. it is a read only bit. hsyncs bit 6 the hsyncs bit reflects the logical state of hsync input. it is a read only bit. coinv bit 5 this clamp output invert bit will invert the clamp output. when it is zero, the clamp output has default positive going pulse as illustrated in figure 10-1 . when it is one, the clamp output is inverted as negative pulse generated. reset clears this bit. hvtst bit 4 this hv test bit is reserved for testing purpose. it can be accessed only in test mode. so user must be careful while developing the program in evs platform. reset clears this bit. sogin bit 3 if the sogin bit is one, the sog pin which is shared with pd3 will be selected as the composite sync input when the comp bit in spcsr register is one. if it is zero, the hsync pin is the default composite input pin when the comp bit is one. reset clears this bit. clampoe bit 2 the clamp output enable bit is set to configure the pd2 pin as the clamp pulse output pin. reset clear this bit. bpor bit 1 the back porch bit defines the triggering edge of clamp output. when it is one, the clamp pulse is generated at the trailing edge of hsync input. when it is zero, the clamp pulse is generated at the leading edge of hsync input. reset clears this bit. sout bit 0 the sout will select the output signals of vsyno and hsyno from the internal free-running counter. when it is zero, the incoming hsync and vsync or extracted vsync 0 7 0000000 6543210 w r spiocr $0011 reset t bpor sout clampoe sogin hvtst coinv hsyncs vsyncs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 53 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary will be output to the hsyno and vsyno pins. when it is one, the free-running 55.556khz hsync with 2us negative pulse and 72.34hz vsync with 108us negative pulse will be generated to the hsyno and vsyno output stages. reset clears this bit. 10.3.3 vertical frequency registers (vfrs) this 13-bit read only register pair contains information of the vertical frame frequency. an internal counter counts the number of internal clocks between two vsync pulses. the most significant 5 bits of counted value will then be transferred to high byte register, $0d, and the least significant 8 bits of counted value is transferred to one intermediate buffer. when the high byte register is read, the 8-bit counted value stored in the intermediate buffer will be uploaded to the low byte register, $0e. so the program must read the high byte register first then low byte register in order to get the complete counted value of one vertical frame. if the counter overflow, the vof flag will be set while the counter values stored in vfr max freq min freq vfr max freq min freq $03c0 130.34 hz 130.07 hz $0823 60.04 hz 59.98 hz $03c1 130.21 hz 129.94 hz $0824 60.01 hz 59.95 hz $03c2 130.07 hz 129.80 hz $0825 59.98 hz 59.92 hz $04e2 100.08 hz 99.92 hz $09c4 50.02 hz 49.98 hz $04e3 100.00 hz 99.84 hz $09c5 50.00 hz 49.96 hz $04e4 99.92 hz 99.76 hz $09c6 49.98 hz 49.94 hz $06f9 70.07 hz 69.99 hz $1ffd 15.266 hz 15.262 hz $06fa 70.03 hz 69.95 hz $1ffe 15.264 hz 15.260 hz $06fb 69.99 hz 69.91 hz $1fff 15.262 hz 15.258 hz 0 7 0000000 6543210 w r vfhr $000d reset t vof 0 0 vf12 vf11 vf10 vf9 vf8 0 7 0000000 6543210 w r vflr $000e reset t vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 54 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary the vfrs registers are meaningless. the data corresponds to the period of one vertical frame. this register can be read to determine if the frame frequency is valid, and to determine the video mode. the msb in the vfhr register will indicate the overflow condition when the period of vsync frame exceeds 64.768ms (lower than 15.258hz). this vof flag is default to be zero and will be update every vertical frame or set when the counter overflows. the frame frequency is calculated by 1/(vfr 1 x 8m s) or 1/(vfr 1 x 16 x tcyc). the table above shows examples for the vertical frequency register, all vfr numbers are in hexadecimal: 10.3.4 hsync frequency registers (hfrs) this 13-bit read-only register pair contains the number of horizontal lines within 32ms and one overflow bit, hover. an internal line counter counts the horizontal sync pulses within 32ms window of every 32.768ms period. the most significant 7 bits of counted value will then be transferred to high byte register, $0f, and the least significant 5 bits of counted value is transferred to one intermediate buffer. when the high byte register is read, the 5- bit counted value stored in the intermediate buffer will be uploaded to the low byte register, $10. so the program must read the high byte register first then low byte register in order to get the complete counted value of horizontal pulses. the hover bit will be set immediately if the number of incoming horizontal sync pulses in 32ms are more than 4095, that means hsync frequency is over 128khz. the hfhr data can be read to determine the number of khz of hsync frequency and the hflr shows the sub-khz value of hsync frequency. this makes user easy to read the frequency of hsync and determine the video mode. 10.4 system operation this module is used mainly for user to determine the video mode of incoming hsync and vsync of various frequency and polarity. it is designed to assist in determining the video mode including dpms modes. the definition of ?o pulses?of dpms standard can be detected when the value of h counter register is less than one or the vof in the vfhr register is set. for the hsync counter value will be updated repeatedly every 32.768ms 0 7 0000000 6543210 w r hfhr $000f reset t hover hfh6 hfh5 hfh4 hfh3 hfh2 hfh1 hfh0 0 7 0000000 6543210 w r hflr $0010 reset t 0 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 55 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary and also we know the valid vsync pulse, more than 40hz, could arrive in shorter time. so it is recommended that user reads the counter value every 32.768ms period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 10: sync processor page 56 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 11: multi-function timer page 57 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 11 multi-function timer 11.1 introduction this module provides miscellaneous function to the mc68HC05BD7. it includes a timer overflow, real-time interrupt, and watchdog functions. also included in the module is the capability of selecting the mode of the maskable external interrupt pin, either edge- triggered mode only or both edge-triggered mode and level-triggered mode. the clock base for this module is derived from bus clock divided by four. for a 2 mhz e (cpu) clock, the clock base is 0.5 mhz. this clock base is then divided by an 8-stage ripple counter to generate the timer overflow. timer overflow rate is thus e/1024. the output of this 8-stage ripple counter then drives one stage divider to generate real time interrupt. hence, the clock base for real time interrupt is e/2,048. real time interrupt rate is selected by rt0 and rt1 bits of multi-function timer control/status register (mftcsr). the interrupt rates are e/2,048, e/(2,048x2), e/(2,048x4), and e/(2,048x8). the selected real time interrupt rate is then divided by 64 to generate cop reset. the cop watchdog timer function is implemented by using a cop counter. the minimum cop reset rates are controlled by rt0 and rt1 of mftcsr. if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop time-out is done by writing a ??to bit 0 of address $3ff0. this write operation resets the divide-by-64 counter stage described in the previous paragraph. the cop counter has to be cleared periodically by software with a period less than cop reset rate. it continues to count even though the cpu is in wait mode. in mc68HC05BD7, the cop is always enabled. 11.2 register there are two registers in the multi-function timer as discussed below. 11.2.1 multi-function timer control/status register note: please don? use bset or bclr to manipulate this register when i-bit is clear, or it will generate abnormal reset. tof bit 7 timer overflow flag indicates if the 8-bit ripple counter overflows. tof is set when the 8-bit counter rolls over from 0 7 0000011 6543210 w r mftcsr $0008 reset t tof rtif tofie rtie irqn rt1 rt0 inhirq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 11: multi-function timer page 58 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary $ff to $00. a cpu interrupt request will be generated if tofie is set. tof is a clearable, read-only status bit. clearing the tof is done by writing a ??to tof. rtif bit 6 real time interrupt flag indicates if the output of the rti circuit goes active. the clock frequency that drives the rti circuit is e/2,048, giving a maximum interrupt period of 1.024 milliseconds at a bus rate of 2 mhz. a cpu interrupt request will be generated if rtie is set. rtif is a clearable, read-only status bit. clearing the rtif is done by writing a ??to rtif. tofie bit 5 when timer over flow interrupt enable (tofie) bit is set, the tof flag is enabled to generate an interrupt request to the cpu. when tofie is cleared, the tof flag is prevented from generating an interrupt request. rtie bit 4 when real time interrupt enable (rtie) is set, the rtif flag is enabled to generate an interrupt request to the cpu. when rtie is cleared, the rtif flag is prevented from generating an interrupt request. irqn bit 3 0 = both level and edge triggering are detected for external interrupt (irq ). 1 = only edge triggering is detected for external interrupt. inhirq bit 2 the inhibit irq bit will inhibit the external interrupt input. when it is set, no active falling edge or low period will be recognized as interrupt request. it is possible for a low state input on the irq pin to be seen as a falling edge event when the inhirq bit changes from one to zero, see figure 4-2 for reference. reset clears this bit. rt1-0 bit 1,0 these two bits are used to define real time interrupt rate as well as cop reset rate as tabulated in table 11-1 . reset sets these two bits for the slowest watchdog reset rate. note that the minimal cop reset period is determined by dividing the cop master clock, which is the real time interrupt clock, by 63(63=64-1). the reason is that cop reset operation is asynchronous to cop master clock edge. therefore it is possible that right after cop reset operation, a cop master clock edge arrives to start counting cop period. the effective count of the divide-by-64 counter is hence 63 rather than 64. rt1, rt0 should only be changed right after cop timer has been reset; otherwise, unpredictable result will occur. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 11: multi-function timer page 59 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary table 11-1: cop reset rates and rti rates 11.2.2 mft timer counter register this 8-bit free-running counter register, mftcr, can be read at location $0009. it is cleared by reset. rt1 rt0 min. cop reset period @ 2 mhz e clock 00 01 10 11 64.512 ms 129.024 ms 258.048 ms 516.096 ms rti period @ 2 mhz 1.024 ms 2.048 ms 4.096 ms 8.192 ms 0 7 0000000 6543210 w r mftcr $0009 reset t mftcr7 mftcr6 mftcr5 mftcr4 mftcr3 mftcr1 mftcr0 mftcr2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 11: multi-function timer page 60 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 12: a/d converter page 61 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 12 a/d converter 12.1 introduction the analog-to-digital converter (adc) system consists of four analog input channels and a single 6-bit d/a converter and comparator, with continuous conversion. a result flag indicates if the comparator output is above or below the analog input. adc is disabled by setting ad5 to ad0 bits of adc control/status register to all 1?. this disable function is mainly for low power application. figure 12-1: structure of a/d converter 12.2 input the adc has four multiplexed input channels. only one of the four channels will be selected by chsl1 and chsl0 bits as analog input. 12.2.1 adc0-adc3 the adc0 to adc3 inputs are multiplexed with the pc2 to pc5 port pins. they are selected as adc input then the corresponding ad0-ad3 bit in the cr2 register is one. the user can use the chsl1 and chsl0 bits to select one of the four channels to do the a/d conversion and get the approximate digital value of each input channel. + - vdd 2r r r r 2r 2r 2r 2r result ad5 ad3 ad2 ad0 adc0 or adc1 or adc2 or adc3 r 2r ad4 2r ad1 r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 12: a/d converter page 62 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 12.3 registers 12.3.1 adc control/status register this read/write register, located at address $14, contains six control bits and one status bit. result - comparator status bit (read only) when set, d/a output 3 analog in. when clear, d/a output 3 analog in. ad5:0 - a/d digital result these bits are written by the user to perform successive approximations in software. when a value causes the result bit to change state from the value immediately before or after it, ad5:0 are considered to be the digital equivalent of the analog input. note that when ad5:0 are all 1?, adc is virtually turned off to minimize power consumption. 12.3.2 adc channel register the adc channel register, located at address $15 contains only two bits. chsl1:chsl0 - channel select bits these two bit will select one of the four adc input channels as analog input source. following table shows its configuration. chsl1:chsl0 = 0 : 0 ==> adc0 chsl1:chsl0 = 0 : 1 ==> adc1 chsl1:chsl0 = 1 : 0 ==> adc2 chsl1:chsl0 = 1 : 1 ==> adc3 0 7 0000000 6543210 w r adcsr $0014 reset t result ad5 ad4 ad3 ad2 ad1 ad0 0 7 0000000 6543210 w r adccr $0015 reset t chsl1 chsl0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 12: a/d converter page 63 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 12.4 program example the following example shows how to convert analog input channel 0 by using binary search method. this approach method will guarantee any conversion can be done within 6 iterations, 98us at 2mhz bus clock. for adcin1 conversion, change #$00 to #$01. adccr is the adc channel register. cr2 equ $0b ; configuration register adccr equ $15 ; adc channel register adcsr equ $14 ; adc control & status register adcdata equ $50 ; ram byte to store the conversion result refh equ $51 ; ram byte to store the high end of conversion refl equ $52 ; ram byte to store the low end of conversion org $1000 lda #$3c sta cr2 ; configure pc2-pc5 as adc inputs lda #$00 sta adccr ; select the input channel lda #$00 sta refl ; initial low end = #$00 lda #$3f sta refh ; initial high end =#$3f dalp lda refh add refl lsra ; a= (refh + refl)/2 sta adcsr ; store the comparison data to d/a cmp refl ; compare the stored value with refl beq done ; if equal, the a is the result digital value brset 7,adcsr,sethi ; check the result flag sta refl ; if lower, set a as the low end of conversion bra dalp sethi sta refh ; if higher, set a as the high end of conversion bra dalp done sta adcdata * input voltage calculation at v dd =5v: adcdata x 0.078125v input (adcdata+1) x 0.078125v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 12: a/d converter page 64 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 13: electrical specifications page 65 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 13 electrical specifications 13.1 maximum ratings (voltages referenced to v ss ) this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either v ss or v dd ). 13.2 thermal characteristics rating symbol value unit supply voltage v dd ?.3 to +7.0 v input voltage v in v ss ?.3 to v dd +0.3 v irq pin v in v ss ?.3 to 2v dd +0.3 v current drain per pin excluding vdd and vss v in 25 ma operating temperature range mc68HC05BD7 (standard) t a 0 to +70 c storage temperature range t stg ?5 to +150 c characteristic symbol value unit thermal resistance plastic q ja 60 c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 13: electrical specifications page 66 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 13.3 dc electrical characteristics (v dd = 5.0 v dc 10%, v ss = 0vdc, t a = 0?c to +70?c, unless otherwise noted) notes: 1. all values shown reflect average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. wait i dd : only timer system and ssp active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source to extal (f osc = 4.2 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on extal. 5. wait i dd : all ports configured as inputs, v il = 0.2 vdc, v ih = v dd -0.2 vdc. 6. wait i dd is affected linearly by the extal capacitance. characteristic symbol min typ max unit output high voltage (i load = -5.0 ma) pa0-pa7, pb0-pb1, pc2-pc7, pwm0-pwm7 v oh v dd ?.8 v output low voltage (i load = 5.0 ma for +5v pins and i load = 10.0 ma for +12v open-drain pins) pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd3, pwm0- pwm7 v ol 0.5 v input high voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd1, reset , irq , extal (ttl level) vsync, hsync, sog sda,scl v ih v ih v ih 0.8 x v dd 2.0 0.8 x v dd v dd v dd v dd v v v input low voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd3, reset , irq , extal (ttl level) vsync, hsync, sog sda,scl v il v ss v ss v ss 0.2 x v dd 0.8 0.2 x v dd v v v supply current (see notes) run wait i dd i dd 8 4 20 8 ma ma i/o ports hi-z leakage current pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd3 i oz 10 m a input current reset, irq, extal, vsync, hsync i in 1 m a capacitance ports (as input or output), reset , irq , extal, xtal hsync, vsync c out c in 12 8 pf pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 13: electrical specifications page 67 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 13.4 control timing (v dd = 5.0 v dc 10%, v ss = 0vdc, t a = 0?c to +70?c, unless otherwise noted ) note: 1. the minimum period t i lil should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 t cyc . characteristic symbol min max units frequency of operation crystal oscillator option external clock source f osc f osc dc 4.2 4.2 mhz mhz internal operating frequency crystal oscillator (f osc /2) external clock (f osc /2) f op f op dc 2.1 2.1 mhz mhz cycle time (1/f op )t cyc 480 ns crystal oscillator start-up time (crystal oscillator option) t oxon 100 ms reset pulse width low t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilih 125 ns irq interrupt pulse period t ilil note 1 t cyc extal pulse width t oh, t ol 100 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 13: electrical specifications page 68 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary 13.5 ddc12ab timing (v dd = 5.0 v dc 10%, v ss = 0vdc, t a = 0?c to +70?c, unless otherwise noted 13.5.1 ddc12ab interface input signal timing 13.5.2 ddc12ab interface output signal timing note: 1. with 200 pf loading on the sda/scl pins parameter symbol min max units start condition hold time t hd.sta 2 t cyc clock low period t low 4 t cyc clock high period t high 4 t cyc data set up time t su.dat 250 ns data hold time t hd.dat 0 ns start condition set up time (for repeated start condition only) t su.sta 2 t cyc stop condition set up time t su.sto 2 t cyc parameter symbol min max units sda / scl rise time (see note 1) t r 1.0 m s sda / scl fall time (see note 1) t f 300 ns data set up time t su.dat t low ?s data hold time t hd.dat 0 ns t hd.sta t low t high t su.dat t hd.dat t su.sto sda scl t su.sta f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 13: electrical specifications page 69 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary 13.6 hsync/vsync input timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 ? c to +70 ? c, unless otherwise noted) parameter symbol min max units vsync input sync pulse t vi.sp 1/2 4096 t cyc hsync input sync pulse t hi.sp 1/2 12 t cyc vsync to vsyno delay (8pf loading) t vvd 30 40 ns hsync to hsyno delay (8pf loading) t hhd 30 40 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 13: electrical specifications page 70 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 14: mechanical specifications page 71 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 14 mechanical specifications 14.1 introduction the mc68HC05BD7 is available in 40-pin dip and 42-pin sdip packages. 14.2 40-pin dip package (case 711-03) 14.3 42-pin sdip package (case 858-01) ! ! ! #! %% ! $" ! ! ! ! ! ! ! ! # ! " 120 40 21 b a c n k m j l hgfd -b- -a- c d 42 pl f k g n j 42 pl m h l ! ! ! ! % ! ! ! # ! " $" 121 42 22 -t- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 14: mechanical specifications page 72 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 15: application diagram page 73 mc68HC05BD7 r ev. 2 . 0 general release specification preliminary section 15 application diagram pa1 pa0 pa2 sda* scl* pwm7** pwm12 adc1 adc0 pwm9* pwm8* pwm5** hsyno vsyno pwm13 pwm6** vsync hsync pwm3** pwm4** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 41 xtal pa5 pa6 pa3 pa4 pb4* pb3* pb2* pb1 pa7 extal pb5* irq pb0 vdd vss reset pwm0** pwm1** pwm2** 21 42 clamp sog reset ic mc68HC05BD7 4mhz 33p 33p 4k7 4k7 4k7 330 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 4k7 4k7 4k7 4k7 100 100 100k 100k 330 330 330 330 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 0.1u 5k 1k7 3k3 10k 5k 1k7 3k3 10k 10k 4u7 100 100 cs0 cs1 cs2 osd wp eeprom ddc pc *note: reset ic is mc34064 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 15: application diagram page 74 general release specification mc68HC05BD7 r ev. 2 . 0 preliminary this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc05bd7grs/h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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